Reducing data dependent jitter utilising adaptive FIR pre-emphasis in 0.18 μm CMOS

Abstract

Due to advances of technology in multimedia applications in recent years, the demand for high user end bandwidth point to point links has increased significantly. Jitter requirements have become ever more stringent with the increase in high speed serial link data rates. The introduced jitter severely degrades the performance of the high speed serial link. This paper introduces an adaptive FIR pre-emphasis technique as a means to alleviate the problem of limited off-chip bandwidth introducing data dependant jitter. Mathematical as well as SPICE simulation results are presented, together with the implemented integrated circuit layouts of the novel 0.18 μm CMOS implementation. Limited results from the experimentally tested IC are also presented and discussed. The adaptive pre-emphasis technique employed results in a simulated data dependant jitter reduction to less than 12.5 % of a unit interval at a data rate of 5 Gb/s and a modelled 30” FR-4 backplane copper channel.