A 5 GHz BiCMOS I/Q VCO with 360° variable phase outputs using the vector sum method

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dc.contributor.advisor Sinha, Saurabh en
dc.contributor.postgraduate Opperman, Tjaart Adriaan Kruger
dc.date.accessioned 2013-09-06T16:01:48Z
dc.date.available 2009-04-08 en
dc.date.available 2013-09-06T16:01:48Z
dc.date.created 2009-04-17 en
dc.date.issued 2009-04-08 en
dc.date.submitted 2009-04-08 en
dc.description Dissertation (MEng)--University of Pretoria, 2009. en
dc.description.abstract This research looks into the design of an integrated in-phase/quadrature (I/Q) VCO operating at 5 GHz. The goal is to design a phase shifter that is implemented at the LO used for RF up conversion. The target application for the phase shifter is towards phased array antennas operating at 5 GHz. Instead of designing multiple VCOs that each deliver a variety of phases, two identical LC-VCOs are coupled together to oscillate at the same frequency and deliver four outputs that are 90 ° out of phase. By varying the amplitudes of the in-phase and quadrature signals independently using VGAs before adding them together, a resultant out-of-phase signal is obtained. A number of independently variable out-of-phase signals can be obtained from these 90 ° out-of-phase signals and this technique is better known as the vector sum method of phase shifting. Control signals to the inputs of the VGAs required to obtain 22.5 ° phase shifts were designed from simulations and are generated using 16-bit DACs. The design is implemented and manufactured using a 0.35 µm SiGe BiCMOS process and the complete prototype IC occupies an area of 2.65 × 2.65 mm2. The I/Q VCO with 360 ° variable phase outputs occupies 1.10 × 0.85 mm2 of chip area and the 16-bit DAC along with its decoding circuitry occupies 0.41 × 0.13 mm2 of chip area. The manufactured quadrature VCO was found to oscillate between 4.12 ~ 4.74 GHz and consumes 23.1 mW from a 3.3 V supply without its buffer circuitry. A maximum phase noise of -78.5 dBc / Hz at a 100 kHz offset and -108.17 dBc / Hz at a 1 MHz offset was measured and the minimum VCO figure of merit is 157.8 dBc / Hz. The output voltages of the 16 bit DAC are within 3.5 % of the design specifications. When the phase shifter is controlled by the 16 DAC signals, the maximum measured phase error of the phase shifter is lower than 10 %. en
dc.description.availability unrestricted en
dc.description.department Electrical, Electronic and Computer Engineering en
dc.identifier.citation a 2009 en
dc.identifier.other C180/eo en
dc.identifier.upetdurl http://upetd.up.ac.za/thesis/available/etd-04082009-171225/ en
dc.identifier.uri http://hdl.handle.net/2263/23858
dc.language.iso en
dc.publisher University of Pretoria en_ZA
dc.rights © University of Pretoria 2009 C180/ en
dc.subject Vector sum method en
dc.subject Variable gain amplifier en
dc.subject Vga en
dc.subject Inductor capacitor en
dc.subject Phase noise en
dc.subject Vco en
dc.subject Silicon germanium en
dc.subject Sige en
dc.subject Lc en
dc.subject Digital-to-analogue converter en
dc.subject Integrated circuit en
dc.subject Ic en
dc.subject Rf en
dc.subject Radio frequency en
dc.subject Local oscillator en
dc.subject Gilbert mixer en
dc.subject Bicmos en
dc.subject Bipolar cmos en
dc.subject Voltage controlled oscillator en
dc.subject Phase shifter en
dc.subject Phased array antenna en
dc.subject Lo en
dc.subject Dac en
dc.subject UCTD en_US
dc.title A 5 GHz BiCMOS I/Q VCO with 360° variable phase outputs using the vector sum method en
dc.type Dissertation en


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