A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance
| dc.contributor.author | Reddy, Reeshen | |
| dc.contributor.author | Sinha, Saurabh | |
| dc.date.accessioned | 2015-10-01T10:05:38Z | |
| dc.date.issued | 2015-04 | |
| dc.description.abstract | This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicongermanium (SiGe) BiCMOS 130 nm technology and achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm2 and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation. | en_ZA |
| dc.description.embargo | 2016-04-30 | |
| dc.description.librarian | hb2015 | en_ZA |
| dc.description.sponsorship | Council for Scientific and Industrial Research. | en_ZA |
| dc.description.uri | http://www.elsevier.com/locate/mejo | en_ZA |
| dc.identifier.citation | Reddy, R & Sinha, S 2015, 'A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance', Microelectronics Journal, vol. 46, no. 4, pp. 310-319. | en_ZA |
| dc.identifier.issn | 0026-2692 (print) | |
| dc.identifier.issn | 1879-2391 (online) | |
| dc.identifier.other | 10.1016/j.mejo.2015.02.001 | |
| dc.identifier.uri | http://hdl.handle.net/2263/50141 | |
| dc.language.iso | en | en_ZA |
| dc.publisher | Elsevier | en_ZA |
| dc.rights | © 2015 Elsevier Ltd. All rights reserved. Notice : this is the author’s version of a work that was accepted for publication in Microelectronics Journal. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Microelectronics Journal, vol. 46, no. 4, pp. 310-319, 2015. doi :10.1016/j.mejo.2015.02.001. | en_ZA |
| dc.subject | BiCMOS integrated circuits | en_ZA |
| dc.subject | Dynamic range | en_ZA |
| dc.subject | Analogue-digital integrated circuits | en_ZA |
| dc.subject | Mixed analogue digital integrated circuits | en_ZA |
| dc.subject | Wideband | en_ZA |
| dc.subject | Digital-to-analogue converter (DAC) | en_ZA |
| dc.subject | Spurious free dynamic range (SFDR) | en_ZA |
| dc.subject | Negative-channel metal-oxide semiconductor (NMOS) | en_ZA |
| dc.title | A 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance | en_ZA |
| dc.type | Postprint Article | en_ZA |