Broich, RenéGrobler, Hans2015-01-192015-01-192015-01Broich, R & Grobler, H 2015, 'Soft-core dataflow processor architecture optimized for radar signal processing', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 1, pp. 43-51.0278-0070 (online)10.1109/TCAD.2014.2363388http://hdl.handle.net/2263/43120Current radar signal processors (RSPs) lack either performance or flexibility. Custom soft-core processors exhibit potential in high-performance signal processing applications, yet remain relatively unexplored in research literature. In this paper, we use an iterative design methodology to propose a novel soft-core streaming processor architecture. The datapaths of this architecture are arranged in a circular pattern, with multiple operands simultaneously flowing between switching multiplexers and functional units each cycle. By explicitly specifying instruction-level parallelism and software pipelining, applications can fully exploit the available computational resources. The proposed architecture exceeds the clock cycle performance of a commercial high-end digital signal processor (DSP) processor by an average factor of 14 over a range of typical operating parameters in an RSP application.en© 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permissionTerms—Circular dataflowProcessor design methodologyRadar signal processor (RSP)Signal processing architectureSoft-core DSPSoft-core processorStreaming architectureTransport-based processorDigital signal processor (DSP)Postprint Article