High-speed Cherry Hooper flash analog-to-digital converter

dc.contributor.authorFaure, Nicolaas Mattheus
dc.contributor.authorSinha, Saurabh
dc.contributor.emailnicolaas.faure@up.ac.zaen_ZA
dc.date.accessioned2017-02-08T07:30:22Z
dc.date.available2017-02-08T07:30:22Z
dc.date.issued2017-01
dc.description.abstractPURPOSE : The 60 GHz unlicensed band is being utilized for high speed wireless networks with data rates in the gigabit range. In order to successfully make use of these high speed signals in a digital system, a high speed analog-to-digital converter (ADC) is required. This paper presents the use of a common collector (CC) input tree and Cherry Hooper differential amplifier to enable analog-to-digital conversion at high frequencies. APPROACH : The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The Cherry Hooper differential amplifier is modified to accommodate the low breakdown voltages of the technology node and used as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM’s 130 nm silicon-germanium (SiGe) bipolar complementary metal–oxide–semiconductor (BiCMOS) 8HP technology node. Measurements were carried out on test printed circuit boards (PCBs) and compared with simulation results. FINDINGS : The use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity (INL) and differential nonlinearity (DNL) was 0.33 least significant bits (LSBs). The prototype ADC had a figure of merit of 42 pJ/sample. ORIGINALITY / VALUE : The prototype ADC results showed that the group delay for the Cherry Hooper comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC Cherry Hooper ADC is capable of achieving an ENOB close to 1.18 for frequencies up to 2 GHz, with 180 mW total power consumption.en_ZA
dc.description.departmentElectrical, Electronic and Computer Engineeringen_ZA
dc.description.librarianhb2017en_ZA
dc.description.urihttp://www.emeraldinsight.com/loi/mien_ZA
dc.identifier.citationNicolaas Faure & Saurabh Sinha (2017) "High-speed Cherry Hooper flash analog-to-digital converter", Microelectronics International, vol. 34, iss. 1, pp. 22-29.en_ZA
dc.identifier.issn1356-5362
dc.identifier.other10.1108/MI-08-2015-0075
dc.identifier.urihttp://hdl.handle.net/2263/58925
dc.language.isoenen_ZA
dc.publisherEmeralden_ZA
dc.rights© Emerald Group Publishing Limited 2017en_ZA
dc.subjectFlash analog-to-digital converter (ADC)en_ZA
dc.subjectCherry Hooper amplifieren_ZA
dc.subjectSilicon Germanium (SiGe)en_ZA
dc.subjectHeterojunction bipolar transistor (HBT)en_ZA
dc.subjectSoftware defined radio (SDR)en_ZA
dc.subjectBipolar complementary metal–oxide–semiconductor (BiCMOS)en_ZA
dc.subjectPrinted circuit boards (PCBs)en_ZA
dc.titleHigh-speed Cherry Hooper flash analog-to-digital converteren_ZA
dc.typePostprint Articleen_ZA

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