A 5 GHz BiCMOS I/Q VCO with 360° variable phase outputs using the vector sum method

dc.contributor.advisorSinha, Saurabhen
dc.contributor.emailtjara@ieee.orgen
dc.contributor.postgraduateOpperman, Tjaart Adriaan Kruger
dc.date.accessioned2013-09-06T16:01:48Z
dc.date.available2009-04-08en
dc.date.available2013-09-06T16:01:48Z
dc.date.created2009-04-17en
dc.date.issued2009-04-08en
dc.date.submitted2009-04-08en
dc.descriptionDissertation (MEng)--University of Pretoria, 2009.en
dc.description.abstractThis research looks into the design of an integrated in-phase/quadrature (I/Q) VCO operating at 5 GHz. The goal is to design a phase shifter that is implemented at the LO used for RF up conversion. The target application for the phase shifter is towards phased array antennas operating at 5 GHz. Instead of designing multiple VCOs that each deliver a variety of phases, two identical LC-VCOs are coupled together to oscillate at the same frequency and deliver four outputs that are 90 ° out of phase. By varying the amplitudes of the in-phase and quadrature signals independently using VGAs before adding them together, a resultant out-of-phase signal is obtained. A number of independently variable out-of-phase signals can be obtained from these 90 ° out-of-phase signals and this technique is better known as the vector sum method of phase shifting. Control signals to the inputs of the VGAs required to obtain 22.5 ° phase shifts were designed from simulations and are generated using 16-bit DACs. The design is implemented and manufactured using a 0.35 µm SiGe BiCMOS process and the complete prototype IC occupies an area of 2.65 × 2.65 mm2. The I/Q VCO with 360 ° variable phase outputs occupies 1.10 × 0.85 mm2 of chip area and the 16-bit DAC along with its decoding circuitry occupies 0.41 × 0.13 mm2 of chip area. The manufactured quadrature VCO was found to oscillate between 4.12 ~ 4.74 GHz and consumes 23.1 mW from a 3.3 V supply without its buffer circuitry. A maximum phase noise of -78.5 dBc / Hz at a 100 kHz offset and -108.17 dBc / Hz at a 1 MHz offset was measured and the minimum VCO figure of merit is 157.8 dBc / Hz. The output voltages of the 16 bit DAC are within 3.5 % of the design specifications. When the phase shifter is controlled by the 16 DAC signals, the maximum measured phase error of the phase shifter is lower than 10 %.en
dc.description.availabilityunrestricteden
dc.description.departmentElectrical, Electronic and Computer Engineeringen
dc.identifier.citationa 2009en
dc.identifier.otherC180/eoen
dc.identifier.upetdurlhttp://upetd.up.ac.za/thesis/available/etd-04082009-171225/en
dc.identifier.urihttp://hdl.handle.net/2263/23858
dc.language.isoen
dc.publisherUniversity of Pretoriaen_ZA
dc.rights© University of Pretoria 2009 C180/en
dc.subjectVector sum methoden
dc.subjectVariable gain amplifieren
dc.subjectVgaen
dc.subjectInductor capacitoren
dc.subjectPhase noiseen
dc.subjectVcoen
dc.subjectSilicon germaniumen
dc.subjectSigeen
dc.subjectLcen
dc.subjectDigital-to-analogue converteren
dc.subjectIntegrated circuiten
dc.subjectIcen
dc.subjectRfen
dc.subjectRadio frequencyen
dc.subjectLocal oscillatoren
dc.subjectGilbert mixeren
dc.subjectBicmosen
dc.subjectBipolar cmosen
dc.subjectVoltage controlled oscillatoren
dc.subjectPhase shifteren
dc.subjectPhased array antennaen
dc.subjectLoen
dc.subjectDacen
dc.subjectUCTDen_US
dc.titleA 5 GHz BiCMOS I/Q VCO with 360° variable phase outputs using the vector sum methoden
dc.typeDissertationen

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