Wideband low noise amplifier for highly sensitive square kilometre array receivers

Abstract

The noise figure (NF) of a low noise amplifier (LNA), which is the first active element in a receiver chain, determines the sensitivity of the receiver and its output signal-to-noise ratio (SNR). For most applications in radio frequency (RF) communications, a sub-1 dB NF is not required. However, applications in radio astronomy, such as the Square Kilometre Array (SKA), require ultra-low NF LNAs because of the extremely low magnitude of radio signals from space. The achievement of the desired sensitivity of the SKA at an adequate cost will require original solutions in wideband LNA technology. For several decades, the technologies mostly used for LNAs in radio astronomy have been based on indium phosphide (InP) and gallium arsenide (GaAs). Extremely low NFs (lower than 0.1 dB) can be achieved with InP transistors at cryogenic temperatures [1]. InP and GaAs semiconductors achieve high unity gain frequency, very low noise and offer passives with good performance. However, InP and GaAs processes have a low integration level, high power consumption and are expensive [1]. Therefore, InP and GaAs devices are not adequate for the SKA and silicon-germanium heterojunction bipolar transistor (SiGe HBT) and CMOS technologies are possible alternatives [1]. The possible alternatives suggest a research gap in the field of low noise RF receivers, which is the topic of this thesis. The inductively degenerated common-source and common-emitter configurations were identified to be the preferred transistor configurations. The cascode configuration was chosen for the LNA topology, owing to its frequency response and to the low coupling between the output and the input. From the literature, the expected NF for an LNA for the SKA is 0.2 dB. However, such requirement being strongly related to the semiconductor process available for fabrication, the requirement was relaxed and it was proposed to develop a design methodology allowing for achieving the minimum possible NF with possibly a sub-1 dB NF. The preferred LNA topology having been identified, the primary research question was formulated as follows: �How can the inductively degenerated common-source/emitter LNA topology be improved to achieve a sub-1 dB NF for highly sensitive differential wideband LNA for the SKA with on-chip inductors at room temperature?� A secondary research question was formulated as follows: �How can semiconductor technologies, passives optimisation, layout and packaging techniques be combined with the adequate LNA topology and design methodology to achieve the required noise performance for the SKA?� The hypothesis of the research was formulated as follows: �If the NF and the input matching of an inductively degenerated common-source or common-emitter cascode LNA with on-chip inductors are optimised, using an improved methodology coupled to enhanced passives and to an adequate semiconductor technology and packaging, a sub-1 dB NF can be achieved on a wideband LNA for the SKA.� The size of transistors remaining equal, the SiGe HBT technology is superior to the CMOS technology in terms of frequency response, noise performance and power gain, which are performance parameters the optimisation of which is generally desired in RF applications. Taking this into account, the SiGe HBT technology was selected for this thesis. A research methodology was proposed and a theoretical analysis was done in order to address the research questions. Results from previous studies show that the noise factor of a common-emitter transistor can be minimised through the direct current biasing of the transistor and the matching of the optimum noise impedance of the amplifier to the impedance of the source. The same results indicate that the noise factor of an integrated common-emitter transistor increases with the width of the emitter, but is weakly related to the length of the emitter and that the optimum source impedance is inversely proportional to the length of the emitter. In this work, it was demonstrated that when identical transistors are connected in parallel, the minimum possible noise factor of the resulting circuit is unchanged, while its optimum source impedance is inversely proportional to the number of transistors in parallel [2]. Therefore, noise matching could be achieved without affecting the noise performance, by changing the length of the emitter or by connecting several identical transistors in parallel [2]. For optimum power transfer from the source to the amplifier, an inductively degenerated common-emitter transistor with an inductor in the base signal path, was proposed. The additional inductors do not significantly affect the noise matching conditions and noise and power matching conditions remain valid when such a circuit is used in a cascode configuration. From this work, the narrow bandwidth of the inductively degenerated common-emitter cascode amplifier was extended by means of an innovative technique that uses the base-collector capacitance to implement coupled resonant circuits with minimum impact on the NF. An output matching network was investigated and it was proposed to use a fourth order Butterworth approximation; the transfer of RF power from the LNA to a 50 � load was optimised by a MATLAB� script. Simulations have shown that the NF was significantly impaired when the base inductor was on-chip, contrary to an external high Q inductor, impeding the achievement of a sub-1 dB NF. The use of an on-chip balun to provide a differential input would also result in a significant increase of the NF, due to the low Q of on-chip inductors. The duplication of a single-ended LNA to provide a differential input, would equally impair the NF and complicate the attainment of a sub-1 dB NF. For these reasons, all related to the low performance of on-chip inductors and to the duplication of noise sources when a single-ended LNA is duplicated, the scope of this research was limited to a single-ended LNA with an external high Q base inductor. For further research, it was proposed to test the initial hypothesis of this research on SiGe HBT technologies having an emitter width smaller than 0.13 _m, such as the Global Foundries 90 nm SiGe HBT and the STMicroelectronics 55 nm BiCMOS055.