The standardisation of the 60 � 80 GHz band by the IEEE802.15.3 task group 3C offers prospects for high speed gigabit wireless applications. This mm-wave band can be used to achieve high data rate transmission in high definition television processing and mobile data applications. Electronic devices utilising the 5th generation cellular standard will begin to use such transceiver chipsets. Nanoscale complementary metal oxide semiconductor (CMOS) technologies have enabled complete mm-wave systems-on-chip (SOC) containing distributed passive, RF active, and CMOS logic circuits. This approach offers the advantage of lower cost, reduced size and lower power consumption. Front-end filters are, however, typically omitted from this system integration due to the low achievable Qfactors of the constituent resonators, which results in high insertion loss and reduced selectivity. There is, therefore, a need for on-chip RF pre-select filters with low insertion loss that are immune to this Q-driven degradation. This research is aimed at the realisation of a miniaturised high performance passive filter in a CMOS technology for mm-wave technologies. Research questions have been formulated where the research outcomes result in a mm-wave passive filter topology. Firstly, the delay line filter is identified as a possible solution for implementation at mm-wave frequencies. Research has been conducted into CMOS planar transmission lines and their associated effects to identify the best suited geometry. Secondly, it is found that the delay performance of a transmission line can be improved by means of introducing geometrical shielding structures. The performance of the CMOS delay lines is evaluated using the quality factor (Q-factor) and group delay as a measure of importance. The delay lines are implemented within a delay line filter topology. The filter is synthesised and simulated in a circuit solver, after which the delay line and complete filter are simulated in a 3D full-wave electromagnetic (EM) simulation tool. The artwork of the complete design is exported, from the integrated circuit (IC) design tool, into the full-wave EM simulator to evaluate and verify the performance of the filter. Three slow-wave coplanar waveguide (CPW) delay lines and a passive mm-wave filter are designed and prototyped using the 0.13 _m bipolar complementary metal oxide semiconductor (BiCMOS) process from GlobalFoundries US as part of the experimental process. The best performing delay line, based on simulation results, has been implemented in a passive filter. The experimental verification confirms the 3D full-wave EM simulation results and answers the proposed research questions. Three CMOS CPW transmission lines have been manufactured and tested. Shielded CPW structures with narrow and wide strip spacings were manufactured to understand the slowwave mechanism. A third fabricated CPW with no shielding structures was used for comparison purposes. Slow-wave geometries have previously been studied, but this research focuses on the Q-factor and delay performance of the slow-wave CPW. Simulation and measured results demonstrate that the narrow strip spacing CPW achieves the greatest group delay at 70 GHz. The narrow strip spacing, wide strip spacing and no strip spacing lines achieve Q-factors of 38.3, 33.64 and 24.9 at 70 GHz respectively, with the narrow strip spacing showing a 34.9 % improvement in Q-factor compared to the no strip spacing CPW. The filter demonstrates a centre frequency of 70.05 GHz, a -3dB bandwidth of 20.74 GHz, a passband attenuation of 5.83 dB and a Q-factor of 4.82. The slow-wave filter compares well with recent literature published on CMOS mm-wave filters.
Dissertation (MEng)--University of Pretoria, 2018.