A design method for distributed element on-chip post-production tunable group delay equalising networks is presented. It is shown that a number of adjustable Darlington C-sections can be used to equalise the group delay of an arbitrary network. The C-sections are implemented in an IBM 0.13 μm BiCMOS process as complementary microstrip slotline-stub all-pass structures and modified to provide post-production tunability. The group delay ripple of a theoretical second-order Butterworth bandpass filter, cascaded with the synthesised all-pass network, is reduced by 43% as proof of concept.
Paper presented at the 2014 International Conference on Actual Problems of Electron Devices Engineering (APEDE), 25-26 Sept. 2014, Saratov, Russia