Soft-core dataflow processor architecture optimized for radar signal processing

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Authors

Broich, René
Grobler, Hans

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Publisher

Institute of Electrical and Electronics Engineers

Abstract

Current radar signal processors (RSPs) lack either performance or flexibility. Custom soft-core processors exhibit potential in high-performance signal processing applications, yet remain relatively unexplored in research literature. In this paper, we use an iterative design methodology to propose a novel soft-core streaming processor architecture. The datapaths of this architecture are arranged in a circular pattern, with multiple operands simultaneously flowing between switching multiplexers and functional units each cycle. By explicitly specifying instruction-level parallelism and software pipelining, applications can fully exploit the available computational resources. The proposed architecture exceeds the clock cycle performance of a commercial high-end digital signal processor (DSP) processor by an average factor of 14 over a range of typical operating parameters in an RSP application.

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Keywords

Terms—Circular dataflow, Processor design methodology, Radar signal processor (RSP), Signal processing architecture, Soft-core DSP, Soft-core processor, Streaming architecture, Transport-based processor, Digital signal processor (DSP)

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Citation

Broich, R & Grobler, H 2015, 'Soft-core dataflow processor architecture optimized for radar signal processing', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 1, pp. 43-51.