Current radar signal processors (RSPs) lack either
performance or flexibility. Custom soft-core processors exhibit
potential in high-performance signal processing applications,
yet remain relatively unexplored in research literature. In this
paper, we use an iterative design methodology to propose a novel
soft-core streaming processor architecture. The datapaths of this
architecture are arranged in a circular pattern, with multiple
operands simultaneously flowing between switching multiplexers
and functional units each cycle. By explicitly specifying
instruction-level parallelism and software pipelining, applications
can fully exploit the available computational resources. The
proposed architecture exceeds the clock cycle performance of
a commercial high-end digital signal processor (DSP) processor
by an average factor of 14 over a range of typical operating
parameters in an RSP application.
Current radar signal processor architectures lack either performance or flexibility in terms of ease of
modification and large design time overheads. Combinations of processors and FPGAs are typically
hard-wired together ...
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