CMOS is well known for its ability to scale. This fact is reflected in the aggressive scaling on a continual basis from the invention of CMOS up to date. As devices are scaled, device performance improves due to shorter channel lengths and more densely packed functions for the same amount of area. In recent years, however, the performance gain obtained through scaling has begun to suffer under the degradation of the associate interconnect performance. As devices become smaller, interconnects need to follow. Unlike transistors, the scaling of interconnects results in higher capacitances and resistances, thereby limiting overall system performance. Trying to alleviate the delay effects results in increased power consumption, especially in global structures such as clock distribution networks. A possible solution to this problem is the use of optical interconnects, which are fast and much less lossy than the electrical equivalents. This dissertation describes an investigation on what future technology nodes will entail in terms of power consumption of clock networks, and what is required for an optical alternative to become feasible. A common clock configuration is used as a basis for comparison, where both electrical and optical networks are designed to component level. Optimisation is done on both to ensure a reasonable comparison, and the results of the respective power consumption components are then compared in order to find the criteria for a feasible optical clock distribution scheme. Copyright
Dissertation (MEng)--University of Pretoria, 2009.