CMOS is arguably the most successful semiconductor technology in electronics history.
This is clear by the constant efforts involved in scaling as the key driver of improving the
performance of ICs to keep up with consumer expectations. However, this trend has lately been
haltered by another on-chip component: the interconnect. As scaling decreases active device
dimensions for a corresponding performance increase, interconnect dimensions suffer under reduction due to increasing capacitance and resistance. One possible solution might be to move the long, power consuming global signal nets into the optical domain. This paper compares predicted electrical versus optical global signal distribution for future nanometre CMOS nodes, based on clock distribution and the associated power consumption.