Abstract:
Layout parasitics significantly impact the performance of mm‐wave microelectronic circuits. These effects may be estimated by including foundry‐qualified pcell interconnect models in schematic with or without additional RC parasitics extraction (RCPE), or by generating an EM simulation (FEM and MoM) of the layout and cosimulating with active device models. In this paper, these methods are compared at by simulating the compression (P1db), gain (S21), and noise figure (NF) of a V‐band LNA in 130 nm SiGe BiCMOS and comparing the results of different simulation approaches to measurements. It is found that the FEM cosimulated results agree better with the measurements than the other methods, providing a maximum error of 0.8 dB in gain, 0.18 dB in NF, and 0.6 dB in P1dB. This is a significant improvement over the errors obtained with pcell‐based schematic (2.6 dB in gain, 0.1 dB in NF, and 2.2 dB in P1db), schematic simulation with RCPE (1.55 dB in gain, 1.15 dB in NF, and 0.8 dB in P1db), and MoM cosimulation (0.67 dB in gain, 0.72 in NF, and 0.67 in P1db). This experiment validates the preference to FEM cosimulation in mm‐wave microelectronic circuits yet would indicate that reasonably accurate first‐iteration results may be obtained through a combined pcell‐RCPE approach with significantly shorter simulation time.
