Differential current sensor linearisation in low-voltage CMOS

Abstract

The viability of low cost, distributed, and autonomous wireless sensor networks is determined by the affordability of the integration and operation of each sensor node. Self-sufficient nodes which harvest energy from the local environment decrease operating and maintenance costs over extended periods of time. This affordability can be achieved by increasing the power usage efficiency of designs implemented in an older and cheaper CMOS process. This circumvents the use of a more compact technology node which trades increased efficiency for cost. The efficiency of power conversion is determined by topology, component quality, control scheme, and internal measurement accuracy. This research focuses on improving internal measurement during the power conversion process, in order to reduce conversion loss from the internal control error. A current sensing integrated circuit was proposed which is insensitive to dominant process characteristics which degrade the performance of other sensing solutions. In particular, the detrimental effect of channel length modulation is compensated for. This compensation is achieved by decoupling the sensor biasing and differential steering pair from being influenced by the external current being measured. Widely used solutions were studied and analysed in the context of implementation in a low cost and low-voltage CMOS process. Key process characteristics which negatively influenced these solutions were identified and formed the basis of developing an improved integrated current sensor. Current research in the literature is tightly focused on improved accuracy without the constraints of process costs, low operating voltage (800mV – 1.2 V), and prevalent second order effects of device operation. A study of the literature on CMOS-based integrated current sensing demonstrates a common goal towards improving sensor accuracy by developing either new topologies or augmenting known topologies. New and augmented topologies focus on novel analogue networks which aim to improve the linearity of CMOS based current sensing. The colloquially named SenseFET circuit is a foundation for many variations of integrated current sensor. This integrated circuit generates an estimate of the current flowing into a DC-DC boost-buck converter by sampling the current sourced into the converters inductor. The low maximum operating voltage of the chosen CMOS process restricts the application of typical published solutions. The sensitivity of other solutions to second order effects limits application as well. The proposed solution is based on such a sampling topology with a focus on achieving linearity in a process with pronounced channel-length modulation effects as well as a relatively low operating voltage. The goal of the improved design is to test if linearity can be improved by developing a circuit which is robust towards second-order process effects. Discreet and integrated boost-buck converters were studied and analysed to form the basis of further sensor developments. An integrated non-inverting converter topology suitable for single rail operation was identified and designed as the system environment for which an integrated sensor would be developed. This would allow for comparison of sensor designs in a known environment, both in simulation and in prototyping of the integrated system. The proposed integrated current sensor was developed analytically before being simulated both mathematically and at transistor gate level. This iterative process was applied to a known design as a performance baseline and to demonstrate the improvements achieved.