MODELLING OF A LOW PHASE NOISE RING OSCILLATOR USING SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTORS

Abstract

In this dissertation, the phase noise performance of single-ended ring oscillators was investigated to determine their suitability in wideband, low phase noise oscillator applications. The main focus was on improving the phase noise performance of the voltage-controlled oscillator (VCO). The VCO was implemented using a custom two-stage single-ended ring oscillator configuration. The research focus was on modelling the phase noise of the VCO. This was accomplished by adapting the impulse sensitivity function for the noise sources present in the circuit. This analysis led to a closed-form phase noise expression defining the process parameters and component values. The expression was verified by way of a simulation comparison generated by SpectreRF and the process design kit supplied by metal-oxide semiconductor implementation service for the design process. A low-noise amplifier based on a complementary metal-oxide semiconductor inverter was characterised and used to amplify the oscillator signal and transform the output impedance of the oscillator to 50 Ω.

The fabricated integrated circuit (IC) was soldered onto a printed circuit board (PCB) and measurements were conducted. It was verified that the direct current-biasing of the prototyped IC was correct, but a 17% variation was found in the passive component values. This, together with a poor ground plane choice on the IC, prohibited the device from working like the simulated version. The simulated oscillator demonstrated a phase noise performance of -80 dBc/Hz at a 1 MHz offset from the carrier. The oscillator also had a tuning range of 72% and consumed on average 4.55 mW, thus providing a VCO figure of merit of -142 dBc/Hz to -182 dBc/Hz, depending on the oscillation frequency. The size of the oscillator on the chip was 80 µm by 100 µm, occupying a total area of 0.008 mm2. This area excluded the size of the bonding pads.