Soft-core dataflow processor architecture optimized for radar signal processing

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dc.contributor.author Broich, René
dc.contributor.author Grobler, Hans
dc.date.accessioned 2015-01-19T09:37:22Z
dc.date.available 2015-01-19T09:37:22Z
dc.date.issued 2015-01
dc.description.abstract Current radar signal processors (RSPs) lack either performance or flexibility. Custom soft-core processors exhibit potential in high-performance signal processing applications, yet remain relatively unexplored in research literature. In this paper, we use an iterative design methodology to propose a novel soft-core streaming processor architecture. The datapaths of this architecture are arranged in a circular pattern, with multiple operands simultaneously flowing between switching multiplexers and functional units each cycle. By explicitly specifying instruction-level parallelism and software pipelining, applications can fully exploit the available computational resources. The proposed architecture exceeds the clock cycle performance of a commercial high-end digital signal processor (DSP) processor by an average factor of 14 over a range of typical operating parameters in an RSP application. en_ZA
dc.description.librarian hb2015 en_ZA
dc.description.uri http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6928471 en_ZA
dc.identifier.citation Broich, R & Grobler, H 2015, 'Soft-core dataflow processor architecture optimized for radar signal processing', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 1, pp. 43-51. en_ZA
dc.identifier.issn 0278-0070 (online)
dc.identifier.other 10.1109/TCAD.2014.2363388
dc.identifier.uri http://hdl.handle.net/2263/43120
dc.language.iso en en_ZA
dc.publisher Institute of Electrical and Electronics Engineers en_ZA
dc.rights © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission en_ZA
dc.subject Terms—Circular dataflow en_ZA
dc.subject Processor design methodology en_ZA
dc.subject Radar signal processor (RSP) en_ZA
dc.subject Signal processing architecture en_ZA
dc.subject Soft-core DSP en_ZA
dc.subject Soft-core processor en_ZA
dc.subject Streaming architecture en_ZA
dc.subject Transport-based processor en_ZA
dc.subject Digital signal processor (DSP) en_ZA
dc.title Soft-core dataflow processor architecture optimized for radar signal processing en_ZA
dc.type Postprint Article en_ZA


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