There exists a need to be able to acquire high data speed over a wide bandwidth. This requires the use of an analogue-to-digital converter (ADC) capable of achieving wide input bandwidth. With the 60 GHz unlicensed band, which has 7 GHz of usable bandwidth, the effective resolution bandwidth of an ADC must be at least 7 GHz. Parallel architectures, such as the flash ADC, are used to obtain fast sampling speeds and are suitable for systems where a wide bandwidth is required. The input bandwidth is reduced as the bit size is increased due to the large parasitic capacitance present at the input of the ADC. The 0.13 ?m IBM 8HP SiGe BiCMOS process provides high speed heterojunction bipolar transistors (HBTs) with cut-off frequencies (fT) up to 200 GHz providing possible operation in the mm-wave region. Amongst other advantages, HBTs have good noise performance characteristics and are discussed in the dissertation.
The focus of the research is to reduce the effect of the parasitic input capacitance of a flash ADC, whilst still maintaining ADC performance at low-GHz range frequencies. In order to improve the input bandwidth a common collector input tree is proposed. The Cherry Hooper differential amplifier is proposed to function as the ADC comparator. The input tree separates the parasitic input capacitances of each comparator thereby reducing the high parasitic input capacitance and improving the bandwidth of the ADC. The Cherry Hooper amplifier can be used as a transimpedance amplifier for mm-wave signals. By connecting the Cherry Hopper amplifier in a differential pair configuration, a comparator can be realised for use in an ADC. The input tree in combination with the Cherry Hooper amplifier could provide high bandwidth and maintain ADC performance at low-GHz frequencies for use in the 60 GHz mm-wave bandwidth frequency. This led to the hypothesis of this research.
Cadence Virtuoso results are presented in this dissertation to support the derived hypothesis. AC simulation results show a gain of approximately 6 dB with a bandwidth up to 30 GHz for a two-bit ADC. Time domain simulation results show digital outputs within the 10/90% range of the 440 mV single ended output swing, up to 5 GHz. A two-bit ADC is also prototyped within the 0.13 ?m 8HP IBM SiGe process in order to affirm the hypothesis. Measurement printed circuit boards (PCBs) were designed and developed to measure various characteristics of the ADC, such as the integral non-linearity (INL) and differential non-linearity (DNL), to determine the effective number of bits (ENOB) and hence the figure of merit (FOM). Measurement results showed INL and DNL results up to 0.33 least significant bits (LSBs), an effective resolution bandwidth (ERBW) up to 2 GHz and an ENOB up to 1.18. Reduction in bandwidth of the implemented system was due to high inductive test leads. The increase in inductance at the test leads lead to oscillations on the comparator outputs and reduced the voltage standing wave ratio. These measured results were confirmed in post layout simulations.
Dissertation (MEng)--University of Pretoria, 2016.